1. Technical Field
This invention generally relates to semiconductor processing and more specifically relates to defect monitoring in semiconductor processing.
2. Background Art
An ongoing concern in semiconductor technology is the maximization of fabrication yield. One factor that leads to a reduction in fabrication yield is the presence of process-induced defects in the semiconductor device. Random defects are typically caused by foreign material (FM), particularly in the form of particles. The result of these defects are frequently circuit failure caused by unwanted opens in conductive lines, shorts between adjacent conductive lines, or shorts between overlying conductive lines.
An analysis of process-induced defects can be very useful in identifying and eliminating yield detractors. However, because of the complexity of modem Very Large Scale Integrated (VLSI) circuits, testing the actual semiconductor devices is very time consuming and costly. Additionally, the information gained from testing the actual devices is limited, as it is often impossible to determine the extent and frequency of the processing defects.
As a result of the above problems, it is preferable to fabricate special semiconductor-processing defect monitors that are dedicated to the analysis of processing defects. These defect monitors are built with structures comparable in sensitivity to defects to those in the VLSI devices, but in such a way that the presence and type of defects are more easily ascertained. These defect monitors are typically constructed at the same time but in a different chip location on the semiconductor substrate than the product VLSI devices, and are discarded once the useful defect information is extracted from them.
These defect monitors can be used either by periodically fabricating a wafer with the defect monitor chips in the production line, replacing some product chips on a sampling basis, or by including the defect monitor in otherwise unused portions of the semiconductor wafer. The latter approaches have the advantage of having the defect monitor fabricated in the exact processing environment as the actual VLSI devices. Thus, the defects in the defect monitors more accurately reflect the defects that exist in the actual VLSI device on a statistical basis with high correlation.
For the same reason, it is desirable that the defect monitors use similar structure types and geometries found in the actual device to ensure equal sensitivity to defects, and are thus preferably manufactured using the same process as the actual device.
Some attempts have been made to use visual inspections to locate defects. While these inspections can reveal the contamination or the presence of FM, they cannot always distinguish between FM that causes electrical failures and those that do not. Additionally, as the size of VLSI devices has decreased and the density of these devices on a wafer has increased, the optical resolutions available are increasingly inadequate to perform this type of inspection quickly and accurately.
Thus, in the prior art defect monitors were limited to either visually locating the number and distribution of defects in a relatively quick in line inspection process, or allowing characterization of the defects in a time consuming, off-line failure analysis of the product chips after final test. Most serious analysis used to identify and isolate the specific defect mechanisms that cause devices failures has been relegated to off-line testing and tedious unlayering of the product chips. Although time consuming, this analysis is a critical tool in characterizing unique and complex defect mechanisms. However, the time required for a detailed failure analysis makes this method unsuitable for in situ (i.e., in-place) testing of the semiconductor wafer during wafer processing.
Therefore what is needed is a defect monitor structure and method that can be used in situ to characterize the type of defect as well as to determine the distribution of these defects.